1. Field of the Invention
The present invention generally relates to semiconductor dynamic random access memories (DRAMs) and, more particularly, to correcting bit errors arising during sleep mode due to a reduced DRAM refresh rate.
2. Description of the Related Art
There are two common families of RAM memory devices used as primary storage directly accessible by the microprocessor. The first, static random access memory devices (SRAMs) are based on flip-flop circuits and retain data as long as power is supplied. The second, dynamic random access memory devices (DRAMs), store data as a function of a charge on a capacitor. The capacitors must constantly be refreshed since the charge dissipates. Both have advantages and disadvantages. DRAMs are relatively inexpensive to fabricate but are slow as compared to SRAMs. SRAMs are therefore typically reserved for use as caches. DRAMs, on the other hand, are relatively inexpensive providing a lower cost per bit and are therefore used commonly as main memory.
In their simplest form, a single DRAM memory cell comprises a single transistor and a single capacitor. Depending on the convention used, if a charge is stored on the capacitor the cell is said to store a 1-bit. If no charge is present, the cell is said to store a 0-bit. Since the charge on the capacitor dissipates over time, DRAM systems require additional overhead circuitry to periodically refresh the charge on the capacitor.
Power conservation is an important consideration in many modern devices. This is particularly true for devices which rely on batteries for their source of power. Many different power conservation schemes have been devised to conserve battery power. One of the most effective conservation methods involves placing the device in a suspended or “sleep” mode when no activity has been detected for some predetermined period of time. Probably the most well know example of a device having a sleep mode is a hand held digital assistant device or a lap top computer. In the case of a lap top computer, during a normal or “active mode”, the battery provides power for a number of separate systems within the lap top computer. For example, a great deal of power is consumed by the display screen and mechanical disk drive systems. During active mode, all of these systems are powered and readily available for use by the CPU. If however, a predetermined time period has elapsed with no user activity (e.g., 5–10 minutes), then the CPU can execute a routine shutting down various systems to enter the sleep mode. Typically in sleep mode, the display screen is powered down as well as the mechanical disk drives thus conserving considerable power. When the user returns to the laptop computer and enters a command, such as striking any key on the keyboard, the CPU restores power to the sleeping components and the user is able to resume activity right where they left off.
However, even during sleep mode, the DRAM memory still requires periodic refreshment in order to retain the data bits stored therein. In an effort to trim even more power consumption, it has been suggested to decrease the refresh cycle rate of the DRAM memory during sleep mode. Unfortunately, a problem arises in that decreasing the refresh rate can cause some data to be lost. That is, if a charge on a particular DRAM memory cell capacitor is allowed to dissipate below a point at which it can still reliably be read, that bit can be lost. This introduces an error in the particular memory byte to which that bit belongs.
This problem has been addressed in U.S. Pat. No. 6,199,139 to Katayama et al., herein incorporated by reference, and commonly assigned with the present application to International Business Machines Corporation (IBM). Katayama is directed to a memory system wherein the DRAM refresh rate is decreased in a sleep mode. An error correction encoding circuit is provided to encode useful data stored in the DRAM with an error correcting code (ECC).
Error correction codes (ECC) can be used to detect and correct errors. These codes typically rely on using additional bits, sometimes referred to as parity bits, encoded with the data bits to carry the error detection and correction information. For example, in a simple binary parity check, a parity bit is a single bit that represents whether the total number of “1s” in a particular data stream is even or odd. If one of the bits in a particular data stream is “flipped”, the parity check bit will detect the error since it will not agree with the odd or even number of 1's in the data stream. More than one parity bit may be used for more complex ECC codes. If enough parity bits are used the error can not only be detected, but also corrected. For example, if four parity bits are used, the first parity bit P1 may be used for the first four bits, the second parity bit P2 used for the second four bits, the third parity bit P3 used for the 1,2,5,6 bits and the fourth parity bit P4 used for the 2,3,6,7 bits. Now, assume that there was an error in the last data bit. In this case, parity bit P1, P3, and P4 would agree. However, parity bit P2 would not agree. Since P2 is the only parity bit not agreeing with the stored word then the error has to be in the 8th bit. This is of course a very simple example. Other codes are known that can correct two or more errors in a data stream.
U.S. Pat. No. 6,199,139 to Katayama, supra, is directed to a DRAM memory system that optimizes a refresh period during a sleep mode. An error correcting code (ECC) encoding circuit is used to encode data stored in the DRAM when entering a sleep mode. An ECC decoding circuit is provided to decode and correct errors each time the refresh operation is required to prevent the loss of data.
However, as is apparent from the above discussion, the use of ECC codes does not come without a price. That is, for each byte of actual data in the DRAM, additional bits are required for the ECC code. These bits require additional storage locations within the DRAM. A way of managing storage space for such additional ECC bits is needed.